The present invention pertains to data transfer between central processing units and more particularly to a circuit for reliably controlling variable size data transmission between three central processing units.
Central processing units (CPUs) can transfer data to other CPUs at a high rate of speed, typically in the microsecond range. A simplified manner of accomplishing this data transfer is for both CPUs to cease any other processing and for one CPU to transmit and the other to receive data. This is very inefficient since both CPUs must simultaneously stop all other tasks in order to accomplish the data transfer. Buffering arrangements have been added between the CPUs in order to remove this inefficiency. As a result, the CPUs must indicate how much data is being transferred via the buffer. This indication is itself transmitted as a data word via the buffer. Buffer transmission of this indication is subject to errors and valuable data may be lost as a result.
A typical solution to this problem includes the addition of a single register which indicates the count of the number of data words being transferred. This register is then incremented by the transmitting CPU as data is put into the buffer and the register is decremented by the receiving CPU as data is removed from the buffer. This situation could result in simultaneous access of the two CPUs. As a result, the count of the number of data words may be in error.
Accordingly, it is the object of the present invention to provide a buffering circuit for reliable data transfer between CPUs.